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CY14B101K
1 Mbit (128K x 8) nvSRAM With Real Time Clock
Features

25 ns, 35 ns, and 45 ns access times Pin compatible with STK17TA8 Data integrity of Cypress nvSRAM combined with full featured Real Time Clock (RTC) Low power, 350 nA RTC current Capacitor or battery backup for RTC Watchdog timer Clock alarm with programmable interrupts Hands off automatic STORE on power down with only a small capacitor STORE to QuantumTrapTM initiated by software, device pin, or on power down RECALL to SRAM initiated by software or on power up Infinite READ, WRITE, and RECALL cycles

High reliability Endurance to 200K cycles Data retention: 20 years at 55C Single 3V operation with tolerance of +20%, -10% Commercial and industrial temperature 48-Pin SSOP package (ROHS compliant)
Functional Description
The Cypress CY14B101K combines a 1 Mbit nonvolatile static RAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM is read and written an infinite number of times, while independent, nonvolatile data resides in the nonvolatile elements. The Real Time Clock function provides an accurate clock with leap year tracking and a programmable high accuracy oscillator. The alarm function is programmable for one time alarm or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control.

Logic Block Diagram
QuantumTrap 1024 x 1024
A5 A6 A7 A8 A9 A 12 A 13 A 14 A 15 A 16
VCC
VCAP VRTCbat VRTCcap
HSB
STORE
POWER CONTROL STORE/ RECALL CONTROL
ROW DECODER
STATIC RAM ARRAY 1024 X 1024
RECALL
SOFTWARE DETECT COLUMN IO
A15 - A 0
DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
INPUT BUFFERS
DQ 1
COLUMN DEC RTC
A 0 A 1 A 2 A 3 A 4 A 10 A 11
x1 x2
INT
MUX
A16 - A 0
OE
CE WE
Cypress Semiconductor Corporation Document Number: 001-06401 Rev. *I
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 24, 2009
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CY14B101K
Pin Configurations
Figure 1. 48-Pin SSOP
V CAP A 16 A 14 A 12 A7 A6 A5 INT A4 NC NC NC V SS NC V RTCbat DQ0 A3 A2 A1 A0 DQ1 DQ2 x1 x2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41
V CC A 15 HSB WE A 13 A8 A9 NC A 11 NC NC NC V SS NC V RTCcap DQ 6 OE A 10 CE DQ7 DQ5 DQ4 DQ3 V CC
48-SSOP
Top View
(Not To Scale)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Table 1. Pin Definitions Pin Name A0 - A16 DQ0 - DQ7 NC WE CE OE X1 X2 VRTCcap VRTCbat INT VSS VCC HSB W E G Alt IO Type Input Input Output No Connect Input Input Input Output Input Description Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM. Bidirectional Data IO Lines. Used as input or output lines depending on operation No Connects. This pin is not connected to the die Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active low OE input enables the data output buffers during READ cycles. Deasserting OE high causes the IO pins to tri-state. Crystal Connection Drives crystal on start up. Crystal Connection for 32.768 kHz crystal.
Power Supply Capacitor Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCbat is used) Power Supply Battery Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCcap is used) Output Ground Input Output Interrupt Output. Program to respond to the clock alarm, the watchdog timer, and the power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain). Ground for the Device. Must be connected to ground of the system. Hardware Store Busy. When LOW this output indicates a Hardware Store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional).
Power Supply Power Supply Inputs to the Device.
VCAP
Power Supply AutoStoreTM Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements.
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CY14B101K
Device Operation
The CY14B101K nvSRAM consists of two functional components paired in the same physical cell. The components are SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The CY14B101K suppots infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. See the "Truth Table For SRAM Operations" on page 22 for a complete description of read and write modes. automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2. AutoStore Mode
V CC V CAP
V CAP
V CC
10k Ohm
WE
SRAM READ
The CY14B101K performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-16 determines which of the 131,072 data bytes are accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (see Figure 8 on page 17). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (see Figure 9 on page 17). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the WRITE cycle and must remain stable until either CE or WE go HIGH at the end of the cycle. The data on the common IO pins DQ0-7 is written into the memory if the data is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Electrical Characteristics on page 15 for the size of the VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on WE to hold it inactive during power up. This pull up is only effective if the WE signal is tri-state during power up. Many MPUs tri-state their controls on power up. Verify this when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation takes place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation took place. Monitor the HSB signal by the system to detect if an AutoStore cycle is in progress.
AutoStore(R) Operation
The CY14B101K stores data to nvSRAM using one of three storage operations: 1. Hardware Store activated by HSB 2. Software Store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101K. During normal operations, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part
Hardware STORE (HSB) Operation
The CY14B101K provides the HSB pin for controlling and acknowledging the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B101K conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin is externally pulled up if it is used to drive other inputs.
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0.1UF
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CY14B101K
SRAM READ and WRITE operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14B101K continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it is allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. During any STORE operation, regardless of how it is initiated, the CY14B101K continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the CY14B101K remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used. The software sequence is clocked with CE controlled READs or OE controlled READs. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations are performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC < VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle automatically initiates and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B101K software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further READs and WRITEs are inhibited until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If it intervenes, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence are performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE cycle
Data Protection
The CY14B101K protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B101K is in a WRITE mode (both CE and WE LOW) at power up, after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brownout conditions.
Noise Considerations
The CY14B101K is a high speed memory and must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
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CY14B101K
Low Average Active Power
CMOS technology provides the CY14B101K the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 shows the relationship between ICC and READ/WRITE Cycle Time. The worst case current consumption is shown for commercial temperature range, VCC = 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14B101K depends on the following items:

Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
The duty cycle of chip enable The overall cycle rate for accesses The ratio of READs to WRITEs The operating temperature The VCC level IO loading
The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product's firmware should not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration and cold or warm boot status, must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. The OSCEN bit in the Calibration register at 0x1FFF8 should be set to 1 to preserve battery life when the system is in storage (see Stopping and Starting the Oscillator on page 7). The Vcap value specified in this data sheet includes a minimum and a maximum value size. The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers who want to use a larger Vcap value to make sure there is extra store charge should discuss their Vcap size selection with Cypress.
Figure 3. Current versus Cycle Time
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CY14B101K
Table 2. Mode Selection CE H L L L WE X H L H OE X L X L A15 - A0 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Not Selected READ SRAM WRITE SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL IO Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Standby Active Active Active ICC2[1, 2, 3]
L
H
L
Active[1, 2, 3]
Notes 1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101K, only the lower 16 lines are used to control software modes. 3. O state depends on the state of OE. The IO table shown is based on OE Low.
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CY14B101K
Real Time Clock Operation
nvTIME Operation
The CY14B101K offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and the clock or timer information registers prevents accessing transitional internal clock data during a READ or WRITE operation. Double buffering also circumvents disrupting normal timing counts or clock accuracy of the internal clock while accessing clock data. Clock and Alarm Registers store data in BCD format. The RTC register addresses for CY14B101K range from 0x1FFF0 to 0x1FFFF. Refer to RTC Register Map[5, 6] on page 11 and Register Map Detail on page 12 for detailed description. The clock oscillator uses very little current to maximize the backup time available from the backup source. Regardless of clock operation with the primary source removed, the data stored in nvSRAM is secure, as it is stored in the nonvolatile elements when power was lost. During backup operation, the CY14B101K consumes a maximum of 300 nA at 2V. The user should choose capacitor or battery values according to the application. Backup time values, based on maximum current specifications, are shown in the following table. Nominal times are approximately three times longer. Table 3. RTC Backup Time Capacitor Value 0.1F 0.47F 1.0F Backup Time 72 hours 14 days 30 days
Clock Operations
The clock registers maintain time up to 9,999 years in one second increments. The user sets the time to any calendar time and the clock automatically keeps track of days of the week, month, leap years, and century transitions. There are eight registers dedicated to the clock functions that are used to set time with a WRITE cycle and to READ time during a READ cycle. These registers contain the Time of Day in BCD format. Bits defined as `0' are currently not used and are reserved for future use by Cypress.
Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, use a 3V lithium; the CY14B101K only sources current from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B101K. The battery capacity is chosen for total anticipated cumulative downtime required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFF8 controls the enable and disable of the oscillator. This active LOW bit is nonvolatile and is shipped to customers in the "enabled" (set to 0) state. To preserve the battery life when the system is in storage, OSCEN bit must be set to `1'. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately 5 seconds (10 seconds maximum) for the oscillator to start. While system power is off, if the voltage on the backup supply (VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail.The CY14B101K has the ability to detect oscillator failure when system power is restored. This is recorded in the OSCF (Oscillator Failed bit) of the Flags register at address 0x1FFF0. When the device is powered on (VCC goes above VSWITCH), the OSCEN bit is checked for "enabled" status. If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms, the OSCF bit is set to "1". The system must check for this condition and then write `0' to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the "Base Time" (see "Setting the Clock" on page 7), which is the value last written to the time keeping registers. The Control or Calibration registers and the OSCEN bit are not affected by the "oscillator failed" condition. The value of OSCF must be reset to `0' when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit "W" (in the flags register at 0x1FFF0) to "1" to enable writes to the Flag register. Write a "0" to the OSCF bit and then reset the write bit to "0" to disable writes.
Reading the Clock
The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. The user should stop internal updates to the CY14B101K time keeping registers before reading clock data, to prevent reading of data in transition. Stopping the internal register updates does not affect clock accuracy. The updating process is stopped by writing a `1' to the read bit `R' (in the flags register at 0x1FFF0), and does not restart until a `0' is written to the read bit. The RTC registers are then read while the internal clock continues to run. After a `0' is written to the read bit (`R'), all CY14B101K registers are simultaneously updated within 20 ms.
Setting the Clock
Setting the write bit `W' (in the flags register at 0x1FFF0) to a `1' stops updates to the time keeping registers and enables the time to be set. The correct day, date, and time are then written into the registers in 24 hour BCD format. The time written is referred to as the `Base Time'. This value is stored in nonvolatile registers and used in calculation of the current time. Resetting the WRITE bit to `0' transfers those values to the actual clock counters, after which the clock resumes normal operation.
Backup Power
The RTC in the CY14B101K is intended for permanently powered operations. Either the VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH, the device switches to the backup power supply.
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CY14B101K
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystal oscillators typically have an error of +20ppm to +35ppm. However, CY14B101K employs a calibration circuit that improves the accuracy to +1/-2 ppm at 25C. This implies an error of +2.5 seconds to -5 seconds per month. The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in Calibration register at 0x1FFF8. The calibration bits occupy the five lower order bits in the Calibration register. These bits are set to represent any value between `0' and 31 in binary form. Bit D5 is a sign bit, where a `1' indicates positive calibration and a `0' indicates negative calibration. Adding counts speeds the clock up and subtracting counts slows the clock down. If a binary `1' is loaded into the register, it corresponds to an adjustment of 4.068 or -2.034 ppm offset in oscillator error, depending on the sign. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. If a binary `1' is loaded into the register, only the first two minutes of the 64 minute cycle is modified. If a binary 6 is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, 4.068 or -2.034 ppm of adjustment per calibration step in the Calibration register. To determine the required calibration, the CAL bit in the Flags register (0x1FFF0) must be set to `1'. This causes the INT pin to toggle at a nominal frequency of 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz indicates a +20 ppm error. Hence, a decimal value of -10 (001010b) must be loaded into the Calibration register to offset this error. Note Setting or changing the Calibration register does not affect the test output frequency. To set or clear CAL, set the write bit "W" (in the flags register at 0x1FFF0) to "1" to enable writes to the Flag register. Write a value to CAL, and then reset the write bit to "0" to disable writes. the match process. Depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. Selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. Selecting all match bits (all 0s) causes an exact time and date match. There are two ways to detect an alarm event: by reading the AF flag or monitoring the INT pin. The AF flag in the flags register at 0x1FFF0 indicates that a date or time match has occurred. The AF bit is set to "1" when a match occurs. Reading the flags or control register clears the alarm flag bit (and all others). A hardware interrupt pin may also be used to detect an alarm event. Note CY14B101K requires the alarm match bit for seconds (0x1FFF2 - D7) to be set to `0' for proper operation of Alarm Flag and Interrupt. Alarm registers are not nonvolatile and, therefore, need to be reinitialized by software on power up. To set, clear or enable an alarm, set the `W' bit (in Flags Register - 0x1FFF0) to `1' to enable writes to Alarm Registers. After writing the alarm value, clear the `W' bit back to "0" for the changes to take effect.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the Watchdog Timer register. The timer consists of a loadable register and a free running counter. On power up, the watchdog time out value in register 0x1FFF7 is loaded into the Counter Load register. Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe (WDS) bit is set to `1'. The counter is compared to the terminal value of `0'. If the counter reaches this value, it causes an internal flag and an optional interrupt output. You can prevent the time out interrupt by setting WDS bit to `1' prior to the counter reaching `0'. This causes the counter to reload with the watchdog time out value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and WDT flag never occur. New time out values are written by setting the watchdog write bit to `0'. When the WDW is `0', new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value. When WDW is `1', writes to bits D5-D0 are ignored. The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the watchdog timer is shown in Figure 4. Note that setting the watchdog time out value to `0' disables the watchdog function. The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out. The flag is set upon a watchdog time out and cleared when the user reads the Flags or Control registers. If the watchdog time out occurs, the user also enables an optional interrupt source to drive the INT pin.
Alarm
The alarm function compares user programmed values of alarm time and date (stored in the registers 0x1FFF1-5) with the corresponding time of day and date values. When a match occurs, the alarm internal flag (AF) is set and an interrupt is generated on INT pin if Alarm Interrupt Enable (AIE) bit is set. There are four alarm match fields - date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to `0' indicates that the corresponding field is used in
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CY14B101K
the output pin driver on INT pin. These two bits are located in the Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the Flags register is read by the user. This mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section.
Figure 4. Watchdog Timer Block Diagram
Oscillator
32,768 KHz
Clock Divider
32 Hz
1 Hz
Counter
Zero Compare
WDF
Interrupt Register
WDS Load Register
D Q
Watchdog Interrupt Enable - WIE. When set to `1', the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs. When WIE is set to `0', the watchdog timer only affects the WDF flag in Flags register. Alarm Interrupt Enable - AIE. When set to `1', the alarm match drives the INT pin and an internal flag. When AIE is set to `0', the alarm match only affects the AF flagin Flags register. Power Fail Interrupt Enable - PFE. When set to `1', the power fail monitor drives the pin and an internal flag. When PFE is set to `0', the power fail monitor only affects the PF flag in Flags register. High/Low - H/L. When set to a `1', the INT pin is active HIGH and the driver mode is push pull. The INT pin drives high only when VCC is greater than VSWITCH. When set to a `0', the INT pin is active LOW and the drive mode is open drain. Active LOW (open drain) is operational even in battery backup mode. Pulse/Level - P/L. When set to a `1' and an interrupt occurs, the INT pin is driven for approximately 200 ms. When P/L is set to a `0', the INT pin is driven high or low (determined by H/L) until the Flags or Control register is read. When an enabled interrupt source activates the INT pin, an external host reads the Flags registers to determine the cause. Remember that all flags are cleared when the register is read. If the INT pin is programmed for Level mode, then the condition clears and the INT pin returns to its inactive state. If the pin is programmed for Pulse mode, then reading the flag also clears the flag and the pin. The pulse does not complete its specified duration if the Flags register is read. If the INT pin is used as a host reset, then the Flags or Control register is not read during a reset.
WDW
Q
write to Watchdog Register
Watchdog Register
Power Monitor
The CY14B101K provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low VCC access. The power monitor is based on an internal band gap reference circuit that compares the VCC voltage to VSWITCH threshold. As described in the "AutoStore(R) Operation" on page 3, when VSWITCH is reached as VCC decays from power loss, a data store operation is initiated from SRAM to the nonvolatile elements, securing the last SRAM data state. Power is also switched from VCC to the backup supply (battery or capacitor) to operate the RTC oscillator. When operating from the backup source, read and write operations to nvSRAM are inhibited and the clock functions are not available to the user. The clock continues to operate in the background. The updated clock data is available to the user tHRECALL delay after VCC is restored to the device (see "AutoStore or Power Up RECALL" on page 19).
Interrupts
The CY14B101K has a Flags register, Interrupt register and Interrupt logic that can signal interrupt to the microcontroller. There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0x1FFF6). In addition, each has an associated flag bit in the Flags register (0x1FFF0) that the host processor uses to determine the cause of the interrupt. The INT pin driver has two bits that specify its behavior when an interrupt occurs. An Interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in Interrupts register is enabled (set to `1'). After an interrupt source is active, two programmable bits, H/L and P/L, determine the behavior of
Flags Register
The Flag register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. These flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts to be informed when a flag is set. These flags are automatically reset once the register is read. The flags register is automatically loaded with the value 00h on power up (except for the OSCF bit. See "Stopping and Starting the Oscillator" on page 7.)
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Figure 5. Interrupt Block Diagram
WDF Watchdog Timer WIE PF Power Monitor VINT H/L AF Clock Alarm AIE PFE P/L Pin Driver
VCC
INT
VSS
WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low
Figure 6. RTC Recommended Component Configuration
DQ 0 A3 A2 A1 A0 C1 RF
Recommended Values Y1 = 32.768KHz RF = 10M Ohm C1 = 0 (install cap footprint, but leave unloaded) C2 = 56 pF + 10% (do not vary from this value)
Y1
X1 X2
Note 4. Schottky diodes, (VF < 0.4V at IF=100mA) are recommended at pins A0 - A3 and DQ0 in applications where undershoot exceeds -0.5V. Please see application note AN49947 for further details.
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C2
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Table 4. RTC Register Map[5, 6] Register 0x1FFFF 0x1FFFE 0x1FFFD 0x1FFFC 0x1FFFB 0x1FFFA 0x1FFF9 0x1FFF8 0x1FFF7 0x1FFF6 0x1FFF5 0x1FFF4 0x1FFF3 0x1FFF2 0x1FFF1 0x1FFF0 WDF 0 0 0 0 0 0 OSCEN (0) WDS (0) WIE (0) M (1) M (1) M (1) M (1) AF 0 WDW (0) AIE (0) 0 0 PFE (0) 0 10s Alarm Date 10s Alarm Hours 10 Alarm Minutes 10 Alarm Seconds 10s Centuries PF OSCF 0 0 0 0 0 BCD Format Data [5] D7 D6 D5 0 0 10s Minutes 10s Seconds Cal Sign (0) D4 10s Months 0 10s Hours 0 D3 D2 Years Months Day Of Month Day of Week Hours Minutes Seconds Calibration (00000) WDT (000000) H/L (1) P/L (0) 0 0 Alarm Day Alarm Hours Alarm Minutes Alarm, Seconds Centuries CAL (0) W (0) R (0) D1 D0 10s Years 10s Day of Month Function/Range Years: 00-99 Months: 01-12 Day of Month: 01-31 Day of Week: 01-07 Hours: 00-23 Minutes: 00-59 Seconds: 00-59 Calibration Values [7] Watchdog [7] Interrupts [7] Alarm, Day of Month: 01-31 Alarm, Hours: 00-23 Alarm, Minutes: 00-59 Alarm, Seconds: 00-59 Centuries: 00-99 Flags [7]
Notes 5. ( ) designates values shipped from the factory. 6. The unused bits of RTC registers are reserved for future use and should be set to `0'. 7. Is a binary value, not a BCD value.
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Table 5. Register Map Detail Time Keeping - Years D7 0x1FFFF D6 10s Years D5 D4 D3 D2 Years D1 D0
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Time Keeping - Months D7 0x1FFFE 0 D6 0 D5 0 D4 10s Month D3 D2 Months D1 D0
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. Time Keeping - Date D7 0x1FFFD 0 D6 0 D5 D4 D3 D2 D1 D0 10s Day of Month Day of Month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1-31. Leap years are automatically adjusted for. Time Keeping - Day D7 0x1FFFC 0 D6 0 D5 0 D4 0 D3 0 D2 D1 Day of Week D0
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date. Time Keeping - Hours D7 0x1FFFB 0 D6 0 D5 10s Hours D4 D3 D2 Hours D1 D0
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23. Time Keeping - Minutes D7 0x1FFFA 0 D6 D5 10s Minutes D4 D3 D2 Minutes D1 D0
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Time Keeping - Seconds D7 0x1FFF9 0 D6 D5 10s Seconds D4 D3 D2 Seconds D1 D0
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0-59.
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Table 5. Register Map Detail (continued) Calibration/Control 0X1FFF8 D7 OSCEN OSCEN D6 0 D5 Calibration Sign D4 D3 D2 Calibration D1 D0
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage.
Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. Sign Calibration These five bits control the calibration of the clock. WatchDog Timer 0x1FFF7 WDS WDW D7 WDS D6 WDW D5 D4 D3 WDT D2 D1 D0
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5-D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to 0 allows bits D5-D0 to be written to the watchdog register when the next write cycle is complete. This function is explained in detail in the "Watchdog Timer" on page 8. Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle. Interrupt Status/Control D7 WIE D6 AIE D5 PFIE D4 0 D3 H/L D2 P/L D1 0 D0 0
WDT
0x1FFF6 WIE AIE PFIE 0 H/L P/L
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag. Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm match only affects the AF flag. Power Fail Enable. When set to 1, the alarm match drives the INT pin and the PF flag. When set to 0, the power fail monitor affects only the PF flag. Reserved for future use High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW. Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L) until the flags register is read. Alarm - Day D7 M D6 0 D5 D4 D3 D2 D1 Alarm Date D0
0x1FFF5
10s Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value. M Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the date value.
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Table 5. Register Map Detail (continued) Alarm - Hours 0x1FFF4 D7 M D6 D5 10s Alarm Hours D4 D3 D2 D1 Alarm Hours D0
Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. Alarm - Minutes 0x1FFF3 D7 M D6 D5 10s Alarm Minutes D4 D3 D2 D1 D0 Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. M Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the minutes value. Alarm - Seconds 0x1FFF2 D7 M D6 D5 10s Alarm Seconds D4 D3 D2 D1 D0 Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds' value. M Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value. Time Keeping - Centuries D7 0x1FFF1 D6 D5 10s Centuries D4 D3 D2 Centuries D1 D0
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries. Flags 0x1FFF0 WDF AF PF OSCF D7 WDF D6 AF D5 PF D4 OSCF D3 0 D2 CAL D1 W D0 R
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power-up. Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power-up. Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared to 0 when the Flags register is read or on power-up. Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0 to clear this condition (Flag). The chip does not clear this flag. This bit survives power cycles. Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up. Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC registers to be transferred to the time keeping counters if the time has been changed (a new base time is loaded). This bit defaults to 0 on power up. Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.
CAL W
R
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND ..........-0.5V to 4.1V Voltage Applied to Outputs in High Z State ....................................... -0.5V to VCC + 0.5V Input Voltage...........................................-0.5V to Vcc + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds).......................................... +260C DC Output Current (1 output at a time, 1s duration) ... 15 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) [8, 9] Parameter ICC1 Description Average VCC Current Test Conditions Commercial tRC = 25 ns tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle Industrial rate. Values obtained without output loads. IOUT = 0 mA. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE WE > (VCC - 0.2V). All other inputs cycling. Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE WE > (VCC - 0.2V). All others VIN < 0.2V or > (VCC-0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz VCC = Max, VSS < VIN < VCC -1 -1 2.0 VSS - 0.5 IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 5V rated 17 2.4 0.4 120 Min Max 65 55 50 70 60 55 6 10 Unit mA mA mA mA
ICC2 ICC3
Average VCC Current during STORE Average VCC Current at tAVAV = 200 ns, 3V, 25C Typical Average VCAP Current during AutoStore Cycle VCC Standby Current
mA mA
ICC4 ISB
3 3
mA mA
IIX IOZ VIH[10] VIL VOH VOL VCAP
Input Leakage Current
+1 +1 VCC + 0.5 0.8
A A V V V V F
Off State Output Leakage VCC = Max, VSS < VIN < VCC, CE or OE > VIH Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Storage Capacitor
Notes 8. The HSB pin has IOUT = -10 A for VOH of 2.4 V, this parameter is characterized but not tested. 9. The INT pin is open drain and does not source or sink current when interrupt register bit D3 is low. 10. VIH changes by 100 mV when VCC > 3.5V.
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Data Retention and Endurance
Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 20 200 Unit Years K
Capacitance
These parameters are guaranteed but not tested. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V Max 7 7 Unit pF pF
Thermal Resistance
These parameters are guaranteed but not tested. Parameter Description Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-SSOP 34.85 16.35 Unit C/W C/W
JA JC
Figure 7. AC Test Loads
R1 577 3.0V OUTPUT 30 pF R2 789 3.0V OUTPUT 5 pF
R1 577
For Tri-state Specs
R2 789
AC Test Conditions
Input Pulse Levels ..................................................0 V to 3 V Input Rise and Fall Times (10% - 90%) ........................ <5 ns Input and Output Timing Reference Levels ................... 1.5 V
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AC Switching Characteristics
Parameter Cypress Parameter tACE tRC
[11]
25 ns Description Min Max
35 ns Min Max
45 ns Min Max Unit
Alt. Parameter tELQV tAVQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH tEHICCL
SRAM Read Cycle Chip Enable Access Time 25 25 12 3 3 10 0 10 0 25 0 35 0 13 0 45 3 3 13 0 15 Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 25 35 35 15 3 3 15 35 45 45 20 45 ns ns ns ns ns ns ns ns ns ns ns tAVAV, tELEH Read Cycle Time
tAA [12] tDOE tOHA [12] tLZCE
[13]
tHZCE [13] tLZOE [13] tHZOE [13] tPU [14] tPD [14]
Figure 8. SRAM Read Cycle 1: Address Controlled [11, 12, 15]
Figure 9. SRAM Read Cycle 2: CE and OE Controlled [11, 15]
Notes 11. WE is HIGH during SRAM Read Cycles. 12. Device is continuously selected with CE and OE both Low. 13. Measured 200 mV from steady state output voltage. 14. These parameters are guaranteed by design and are not tested. 15. HSB must remain HIGH during READ and WRITE cycles.
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AC Switching Characteristics (continued)
Parameter Cypress Parameter tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [13, 16] tLZWE
[13]
25 ns Description Min Max
35 ns Min Max
45 ns Min Max Unit
Alt. Parameter tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX
SRAM Write Cycle Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 3 25 20 20 10 0 20 0 0 10 3 35 25 25 12 0 25 0 0 13 3 45 30 30 15 0 30 0 0 15 ns ns ns ns ns ns ns ns ns ns
Figure 10. SRAM Write Cycle 1: WE Controlled [15, 17]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 11. SRAM Write Cycle 2: CE Controlled
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Notes 16. If WE is Low when CE goes Low, the outputs remain in the High Impedance State. 17. CE or WE are greater than VIH during address transitions.
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AutoStore or Power Up RECALL
Parameter tHRECALL [18] tSTORE
[19, 20]
Description Power Up RECALL Duration STORE Cycle Duration Commercial Industrial
CY14B101K Min Max 40 12.5 15 2.65 150
Unit ms ms ms V s
VSWITCH tVCCRISE
Low Voltage Trigger Level VCC Rise Time
Figure 12. AutoStore/Power Up RECALL
VCC VSWITCH
STORE occurs only if a SRAM write has happened
No STORE occurs without atleast one SRAM write
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
Read & Write Inhibited
tHRECALL
Notes 18. tHRECALL starts from the time VCC rises above VSWITCH. 19. If an SRAM Write does not taken place since the last nonvolatile cycle, no STORE takes place. 20. Industrial Grade Devices require 15 ms Max.
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Software Controlled STORE/RECALL Cycles [21, 22]
Parameter tRC tSA tCW tHA tRECALL Alt. Parameter tAVAV tAVEL tELEH tEHAX Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration 25 ns Min 25 0 20 1 170 Max 35 0 25 1 170 35 ns Min Max 45 0 30 1 170 45 ns Min Max Unit ns ns ns ns s
Figure 13. CE Controlled Software STORE/RECALL Cycle [22]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
tSA
CE
tSCE tHA
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
Figure 14. OE Controlled Software STORE/RECALL Cycle [22]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
CE
tSA
OE
tSCE
tHA
DQ (DATA)
DATA VALID
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Notes 21. The software sequence is clocked with CE controlled or OE controlled READs. 22. The six consecutive addresses are read in the order listed in the Table 2 on page 6. WE is HIGH during all six consecutive cycles.
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Hardware STORE Cycle
Parameter tDELAY [25] tPHSB tHLHX Alt. Parameter Description Time Allowed to Complete SRAM Cycle Hardware STORE Pulse Width CY14B101K Min 1 15 Max 70 Unit s ns
Figure 15. Hardware STORE Cycle
Soft Sequence Commands
Parameter tSS [22, 24] Description Soft Sequence Processing Time Figure 16. Soft Sequence Processing [22, 24] CY14B101K Min Max 70 Unit s
Notes 23. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 24. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command. 25. Read and Write cycles in progress before HSB are given this amount of time to complete.
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RTC Characteristics
Parameter IBAK
[26]
Description RTC Backup Current
Test Conditions Commercial Industrial
Min
Max 300 350
Unit nA nA V V sec sec
VRTCbat VRTCcap tOCS
[27] [28]
RTC Battery Pin Voltage RTC Capacitor Pin Voltage RTC Oscillator Time to Start At Min Temperature from Power up or Enable At 25C Temperature from Power up or Enable
1.8 1.2
3.3 2.7 10 5
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations. CE H L L L WE X H H L OE X L H X Inputs and Outputs High Z Data Out (DQ0-DQ7); High Z Data in (DQ0-DQ7); Read Output Disabled Write Mode Deselect/Power down Power Standby Active Active Active
Notes 26. From either VRTCcap or VRTCbat. 27. Typical = 3.0V during normal operation. 28. Typical = 2.4V during normal operation.
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Part Numbering Nomenclature CY 14 B 101 K - SP 25 X C T
Option: T - Tape and Reel Blank - Std. Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C) Pb-Free Package: SP - 48 SSOP
Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns
Data Bus: K - x8 + RTC Density: 101 - 1 Mb
Voltage: B - 3.0V
NVSRAM 14 - AutoStore + Software Store + Hardware Store
Cypress
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Ordering Information
All the below mentioned parts are Pb-free. Please contact your local Cypress sales representative for availability of these parts. Speed (ns) 25 Ordering Code CY14B101K-SP25XC CY14B101K-SP25XCT CY14B101K-SP25XI CY14B101K-SP25XIT 35 CY14B101K-SP35XC CY14B101K-SP35XCT CY14B101K-SP35XI CY14B101K-SP35XIT 45 CY14B101K-SP45XC CY14B101K-SP45XCT CY14B101K-SP45XI CY14B101K-SP45XIT 51-85061 48-pin SSOP Industrial 51-85061 48-pin SSOP Commercial 51-85061 48-pin SSOP Industrial 51-85061 48-pin SSOP Commercial 51-85061 48-pin SSOP Industrial Package Diagram 51-85061 Package Type 48-pin SSOP Operating Range Commercial
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Package Diagrams
Figure 17. 48-Pin Shrunk Small Outline Package (51-85061)
51-85061-*C
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Document History Page
Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Document Number: 001-06401 REV. ** *A *B ECN NO. 425138 437321 471966 Orig. of Change TUP TUP TUP Submission Date See ECN See ECN See ECN New data sheet Show data sheet on External Web Changed ICC3 from 5 mA to 10 mA Changed ISB from 2 mA to 3 mA Changed VIH(min) from 2.2V to 2.0V Changed tRECALL from 40 ms to 100 ms Changed Endurance from 1 million Cycles to 500K Cycles Changed Data Retention from 100 years to 20 years Added Soft Sequence Processing Time Waveform Updated Part Numbering Nomenclature and Ordering Information Added RTC Characteristics Table Added RTC Recommended Component Configuration Changed from Advance to Preliminary Changed the term "Unlimited" to "Infinite" Changed Endurance from 500K Cycles to 200K Cycles Added temperature spec. to Data Retention - 20 years at 55xC Removed Icc1 values from the DC table for 25 ns and 35 ns Industrial Grade Changed Icc2 value from 3 mA to 6 mA in the DC Table Added a footnote on VIH Added footnote 18 related to using the software command Changed VSWITCH(min) from 2.55V to 2.45V Updated Part Nomenclature Table and Ordering Information Table Removed VSWITCH(min) specification from the AutoStore/Power Up RECALL Table Changed tGLAX specification from 20 ns to 1 ns Added tDELAY(max) specification of 70 ms in the Hardware STORE Cycle Table Removed tHLBL specification Changed tSS specification form 70 ms (min) to 70 ms (max) Changed VCAP(max) from 57 mF to 120 mF Added footnote 7 related to HSB Added footnote 8 related to INT pin Changed tGLAX to tGHAX Removed ABE bit from interrupt register Changed from Preliminary to Final Added Note 5 regarding the W bit in the Flag register Updated Ordering Information Table Added Pinout diagram and Pin definition Table Move to external web Description of Change
*C
503272
PCI
See ECN
*D
597002
TUP
See ECN
*E
688776
VKN
See ECN
*F
1349963
UHA/SFV
See ECN
*G *H
1739984 2427986
vsutmp8/AESA GVCH/PYRS
See ECN 04/23/08
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Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Document Number: 001-06401 REV. *I ECN NO. 2663934 Orig. of Change GVCH/PYRS Submission Date 02/24/09 Description of Change Updated Features Updated pin definition of WE Removed AutoStore enable/disable section Added Best practices Updated "Reading the clock", "Backup Power", "Stopping and starting the Oscillator" and "Alarm" descriptions under RTC operation Modified "Figure 4. RTC Recommended Component Configuration" Added footnotes 4, 5 and 6 Added default values to RTC Register Map" table Updated flag register description in Register Map Detail" table Added Industrial specs for 25ns and 35ns speed Changed VIH from Vcc+0.3 to Vcc+0.5 Added "Data Retention and Endurance" table on page 15 Added Thermal resistance values Added alternate parameters in the AC switching characteristics table Renamed tOH to tOHA Changed tHRECALL from 20 to 40ms Changed tRECALL spec from 100s to 170s (Including tss of 70us) Renamed tAS to tSA Renamed tGHAX to tHA Updated Figure 13, 14, 15 and 16 Renamed tHLHX to tPHSB Added truth table for SRAM operations
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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(c) Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06401 Rev. *I
Revised February 24, 2009
Page 28 of 28
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